Renesas SH7641 - Manual (Page 896)

Section 23 I/O Ports
Rev. 4.00 Sep. 14, 2005 Page 846 of 982
REJ09B0023-0400
23.2.2 Port B Data Register (PBDR)
PBDR is a 9-bit readable/writable register with seven reserved bits that stores data for pins PTB8
to PTB0. PBDR is initialized to H'0000 by a power-on reset, but it retains its previous value by a
manual reset, in standby mode, or in sleep mode.
Bit Bit Name
Initial
Value R/W
Description
15 to 9  All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
7 PB7DT 0 R/W
6 PB6DT 0 R/W
5 PB5DT 0 R/W
4 PB4DT 0 R/W
3 PB3DT 0 R/W
2 PB2DT 0 R/W
1 PB1DT 0 R/W
0 PB0DT 0 R/W
Bits PB8DT to PB0DT correspond to pins PTB8 to
PTB0. When the pin function is general output port, the
value of the corresponding bit in PBDR is returned
directly by reading the port. When the function is
general input port, the corresponding pin level is read
by reading the port. Table 23.2 shows the function of
PBDR.
Table 23.2 Port B Data Register (PBDR) Read/Write Operations
PBnMD2 PBnMD1 Pin State Read Write
0 0 Input Pin state Data is written to PBDR, but does not affect
pin state.
1 Output PBDR value Data is written to PBDR and the value is
output from the pin.
1 0 Reserved
 
1 Other functions Pin state Data is written to PBDR, but does not affect
pin state.
(n = 0 to 8)