Renesas SH7641 - Manual (Page 357)

Section 12 Bus State Controller (BSC)
Rev. 4.00 Sep. 14, 2005 Page 307 of 982
REJ09B0023-0400
• CS3WCR
Bit Bit Name
Initial
Value R/W Description
31 to 15  All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
14
13
WTRP1*
WTRP0
0
0
R/W
R/W
Number of Auto-Precharge Completion Wait Cycles
Specify the number of minimum precharge completion
wait cycles during the periods shown below.
• From the start of auto-precharge to issuing of the
ACTV command for the same bank
• From issuing of the PRE/PALL command to issuing
of the ACTV command for the same bank
• Until entering the power-down mode or deep
power-down mode
• From issuing of the PALL command to issuing of
the REF command in auto refreshing
• From issuing of the PALL command to issuing of
the SELF command in self refreshing
The setting for areas 2 and 3 is common.
00: No cycle
01: 1 cycle
10: 2 cycles
11: 3 cycles
12
 0
R Reserved
This bit is always read as 0. The write value should
always be 0.
11
10
WTRCD1
WTRCD0
0
1
R/W
R/W
Number of Wait Cycles between ACTV Command and
READ(A)/WRIT(A) Command
Specify the minimum number of wait cycles from
issuing the ACTV command to issuing the
READ(A)/WRIT(A) command. The setting for areas 2
and 3 is common.
00: No cycle
01: 1 cycle
10: 2 cycles
11: 3 cycles