Renesas SH7641 - Manual (Page 902)

Section 23 I/O Ports
Rev. 4.00 Sep. 14, 2005 Page 852 of 982
REJ09B0023-0400
23.5.1 Register Description
Port E has the following register.
• Port E data register (PEDR)
23.5.2 Port E Data Register (PEDR)
PEDR is a 16-bit readable/writable register that stores data for pins PTE15 to PTE0. The PEDR is
initialized to H'0000 by a power-on reset, but it retains its previous value by a manual reset, in
standby mode, or in sleep mode.
Bit Bit Name
Initial
Value R/W
Description
15 PE15DT 0 R/W
14 PE14DT 0 R/W
13 PE13DT 0 R/W
12 PE12DT 0 R/W
11 PE11DT 0 R/W
10 PE10DT 0 R/W
9 PE9DT 0 R/W
8 PE8DT 0 R/W
7 PE7DT 0 R/W
6 PE6DT 0 R/W
5 PE5DT 0 R/W
4 PE4DT 0 R/W
3 PE3DT 0 R/W
2 PE2DT 0 R/W
1 PE1DT 0 R/W
0 PE0DT 0 R/W
Bits PE15DT to PE0DT correspond to pins PTE15 to
PTE0. When the pin function is general output port, the
value of the corresponding PEDR bit in PEDR is
returned directly by reading the port. When the function
is general input port, the corresponding pin level is read
by reading the port. Table 23.5 shows the function of
PEDR.