Renesas SH7641 - Manual (Page 464)

Section 13 Direct Memory Access Controller (DMAC)
Rev. 4.00 Sep. 14, 2005 Page 414 of 982
REJ09B0023-0400
Bit Bit Name
Initial
Value R/W Descriptions
2 IE 0 R/W Interrupt Enable
This bit specifies whether or not an interrupt request is
generated to the CPU at the end of the DMA transfer.
Setting this bit to 1 generates an interrupt request
(DEI) to the CPU when TE bit is set to 1.
0: Interrupt request is not generated
1: Interrupt request is generated
1 TE 0 R/W* Transfer End Flag
This bit shows that DMA transfer ends. TE is set to 1
when data transfer ends when DMATCR becomes
to 0.
The TE bit is not set to 1 in the following cases.
• DMA transfer ends due to a NMI interrupt or DMA
address error before DMATCR becomes to 0.
• DMA transfer is ended by clearing the DE bit and
DME bit in DMA operation register (DMAOR).
Even if the DE bit is set to 1 while this bit is set to 1,
transfer is not enabled.
0: During the DMA transfer or DMA transfer has been
interrupted
1: Data transfer ends by the specified count (DMACTR
= 0)
[Clearing condition]
Writing 0 after TE = 1 read