Renesas SH7641 - Manual (Page 545)

Section 16 I 2 C Bus Interface 2 (IIC2)
Rev. 4.00 Sep. 14, 2005 Page 495 of 982
REJ09B0023-0400
TDRE
Data n
TEND
ICDRS
ICDRR
1 9 2 3 4 5 6 7 8 9
TRS
ICDRT
A
SCL
(Master output)
SDA
(Master output)
SDA
(Slave output)
SCL
(Slave output)
Bit 7
Slave transmit mode
Slave receive
mode
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
A
[3] Clear TEND
[5] Clear TDRE [4] Read ICDRR (dummy read)
after clearing TRS
User
processing
Figure 16.10 Slave Transmit Mode Operation Timing (2)