Renesas SH7641 - Manual (Page 308)

Section 11 User Break Controller (UBC)
Rev. 4.00 Sep. 14, 2005 Page 258 of 982
REJ09B0023-0400
4. When an instruction fetch cycle is set for channel B, the break data register B (BDRB) is
ignored. Therefore, break data cannot be set for the break of the instruction fetch cycle.
5. If the I bus is set for a break of an instruction fetch cycle, the condition is determined for the
instruction fetch cycles on the I bus. For details, see 5 in section 11.3.1, Flow of the User
Break Operation.
11.3.3 Break on Data Access Cycle
1. If the L bus is specified as a break condition for data access break, condition comparison is
performed for the logical addresses (and data) accessed by the executed instructions, and a
break occurs if the condition is satisfied. If the I bus is specified as a break condition, condition
comparison is performed for the physical addresses (and data) of the data access cycles that are
issued on the I bus by all bus masters including the CPU, and a break occurs if the condition is
satisfied. For details on the CPU bus cycles issued on the I bus, see 5 in section 11.3.1, Flow of
the User Break Operation.
2. The relationship between the data access cycle address and the comparison condition for each
operand size is listed in table 11.3.
Table 11.3 Data Access Cycle Addresses and Operand Size Comparison Conditions
Access Size Address Compared
Longword Compares break address register bits 31 to 2 to address bus bits 31 to 2
Word Compares break address register bits 31 to 1 to address bus bits 31 to 1
Byte Compares break address register bits 31 to 0 to address bus bits 31 to 0
This means that when address H'00001003 is set in the break address register (BARA or
BARB), for example, the bus cycle in which the break condition is satisfied is as follows
(where other conditions are met).
Longword access at H'00001000
Word access at H'00001002
Byte access at H'00001003
3. When the data value is included in the break conditions on channel B:
When the data value is included in the break conditions, either longword, word, or byte is
specified as the operand size of the break bus cycle register B (BBRB). When data values are
included in break conditions, a break is generated when the address conditions and data
conditions both match. To specify byte data for this case, set the same data in two bytes at bits
15 to 8 and bits 7 to 0 of the break data register B (BDRB) and break data mask register B
(BDMRB). When word or byte is set, bits 31 to 16 of BDRB and BDMRB are ignored. Set the