Renesas SH7641 User Manual
Page 241
Section 7 Cache
Rev. 4.00 Sep. 14, 2005 Page 191 of 982
REJ09B0023-0400
Data Array Read: The data specified by L (bits 3 and 2) in the address is read from the entry
address specified by the address and the entry corresponding to the way.
Data Array Write: The longword data specified by the data is written to the position specified by
L (bits 3 and 2) in the address from the entry address specified by the address and the entry
corresponding to the way.
1. Address array access
(a) Address specification
Read access
Write access
(b) Data specification (both read and write accesses)
2. Data array access (both read and write accesses)
(a) Address specification
31
24
23
14
13
12
11
4
3
0
1111 0000
*…………*
*…………*
*…………*
0 0 0
0 0 0
W
Entry
31
24
23
14
13
12
11
4
3
0
1111 0000
W
Entry
2
A
31 30 29
10
4
3
0
LRU
2
X
0
0
0
X
9
Address tag (28 to 10)
U
V
1
31
24
23
14
13
12
11
4
3
0
1111 0001
W
Entry
0 0
1
2
L
(b) Data specification
31
0
Longword
*: Don't
care
bit
X: 0 for read, don't care for write
[Legend]
0
2
Figure 7.4 Specifying Address and Data for Memory-Mapped Cache Access