Renesas SH7641 - Manual (Page 125)

Section 2 CPU
Rev. 4.00 Sep. 14, 2005 Page 75 of 982
REJ09B0023-0400
Instruction
Instruction Code
Operation Execution
States
T Bit
SUBV Rm,Rn 0011nnnnmmmm1011 Rn–Rm → Rn, Underflow → T 1 Underflow
Notes: 1. The normal minimum number of execution cycles is two, but five cycles are required
when the operation result is read from the MAC register immediately after the
instruction.
2. The normal minimum number of execution cycles is one, but three cycles are required
when the operation result is read from the MAC register immediately after the MUL
instruction.
Logic Operation Instructions
Table 2.21 Logic Operation Instructions
Instruction
Instruction Code
Operation Execution
States
T Bit
AND Rm,Rn 0010nnnnmmmm1001 Rn & Rm → Rn 1 —
AND #imm,R0 11001001iiiiiiii R0 & imm → R0 1 —
AND.B #imm,@(R0,GBR) 11001101iiiiiiii (R0 + GBR) & imm →
(R0 + GBR)
3 —
NOT Rm,Rn 0110nnnnmmmm0111 ~Rm → Rn 1 —
OR Rm,Rn 0010nnnnmmmm1011 Rn | Rm → Rn 1 —
OR #imm,R0 11001011iiiiiiii R0 | imm → R0 1 —
OR.B #imm,@(R0,GBR) 11001111iiiiiiii (R0 + GBR) | imm →
(R0 + GBR)
3 —
TAS.B @Rn 0100nnnn00011011 If (Rn) is 0, 1 → T;
1 → MSB of (Rn)
4 Test
result
TST Rm,Rn 0010nnnnmmmm1000 Rn & Rm; if the result
is 0, 1
→ T
1 Test
result
TST #imm,R0 11001000iiiiiiii R0 & imm; if the result
is 0, 1
→ T
1 Test
result
TST.B #imm,@(R0,GBR) 11001100iiiiiiii (R0 + GBR) & imm;
if the result is 0, 1
→ T
3 Test
result
XOR Rm,Rn 0010nnnnmmmm1010 Rn ^ Rm → Rn 1 —
XOR #imm,R0 11001010iiiiiiii R0 ^ imm → R0 1 —
XOR.B #imm,@(R0,GBR) 11001110iiiiiiii (R0 + GBR) ^ imm →
(R0 + GBR)
3 —