Renesas SH7641 - Manual (Page 527)

Section 16 I 2 C Bus Interface 2 (IIC2)
Rev. 4.00 Sep. 14, 2005 Page 477 of 982
REJ09B0023-0400
Bit Bit Name
Initial
Value R/W Description
5
4
MST
TRS
0
0
R/W
R/W
Master/Slave Select
Transmit/Receive Select
In master mode with the I 2 C bus format, when
arbitration is lost, MST and TRS are both reset by
hardware, causing a transition to slave receive mode.
Modification of the TRS bit should be made between
transfer frames.
When seven bits after the start condition is issued in
slave receive mode match the slave address set to
SAR and the eighth bit is set to 1, TRS is automatically
set to 1. If an overrun error occurs in master receive
mode with the clocked synchronous serial format, MST
is cleared and the mode changes to slave receive
mode.
Operating modes are described below according to
MST and TRS combination. When clocked
synchronous serial format is selected and MST 1,
clock is output.
00: Slave receive mode
01: Slave transmit mode
10: Master receive mode
11: Master transmit mode
3
2
1
0
CKS3
CKS2
CKS1
CKS0
0
0
0
0
R/W
R/W
R/W
R/W
Transfer Clock Select 3 to 0
These bits are valid only in master mode. These bits
should be set according to the necessary transfer rate.
For details of transfer rate, see table 16.2.