Renesas SH7641 - Manual (Page 154)

Section 3 DSP Operation
Rev. 4.00 Sep. 14, 2005 Page 104 of 982
REJ09B0023-0400
3.1.2 ALU Integer Operations
Figure 3.6 shows the ALU integer arithmetic operation flow. Table 3.3 shows the variation of this
type of operation. The correspondence between each operand and registers is the same as ALU
fixed-point operations as shown in table 3.2.
39 31 0
Source 1
0
Destination
ALU
DSR
GT Z N V DC
0
Source 2
Ignored
Cleared
Guard
39 31
39 31
Guard
Guard
Figure 3.6 ALU Integer Arithmetic Operation Flow
Table 3.3 Variation of ALU Integer Operations
Mnemonic Function Source 1 Source 2 Destination
PINC Increment by 1 Sx +1 Dz
+1 Sy Dz
PDEC Decrement by 1 Sx −1 Dz
−1 Sy Dz
Note: The ALU integer operations are basically 24-bit operation, the upper 16 bits of the base
precision and 8 bits of the guard bits parts. So the signed bit is copied to the guard-bit parts
when a register not providing the guard-bit parts is specified as the source operand. When
a register not providing the guard-bit parts is specified as a destination operand, the upper
word excluding the guard bits of the operation result are input into the destination register.