Renesas SH7641 - Manual (Page 551)

Section 16 I 2 C Bus Interface 2 (IIC2)
Rev. 4.00 Sep. 14, 2005 Page 501 of 982
REJ09B0023-0400
16.4.7 Noise Filter
The logic levels at the SCL and SDA pins are routed through noise filters before being latched
internally. Figure 16.17 shows a block diagram of the noise filter circuit.
The noise filter consists of three cascaded latches and a match detector. The SCL (or SDA) input
signal is sampled on the system clock. When NF2CYC is set to 0, this signal is not passed forward
to the next circuit unless the outputs of both latches agree. When NF2CYC is set to 1, this signal is
not passed forward to the next circuit unless the outputs of three latches agree. If they do not
agree, the previous value is held.
SCL or SDA
input signal
Internal
SCL or SDA
signal
Sampling clock
Sampling
clock
Peripheral clock
cycle
C
Latch
Q D
C
Latch
Q D
Match
detector
C
Latch
Q D
Match
detector
NF2CVC
1
0
Figure 16.17 Block Diagram of Noise Filter