Renesas SH7641 - Manual (Page 56)

Section 1 Overview
Rev. 4.00 Sep. 14, 2005 Page 6 of 828
REJ09B0023-0400
Items Specification
Compare match timer
(CMT) • 16-bit counter × 2 channels
• Selection of four clocks
• Interrupt request or DMA transfer request can be generated by
compare-match
Serial communication
interface with FIFO
(SCIF) • 3 channels
• Asynchronous mode or clock synchronous mode can be selected
• Simultaneous transmission/reception (full-duplex) capability
• Built-in dedicated baud rate generator
• Separate 16-stage FIFO registers for transmission and reception
• Dedicated Modem control function (Asynchronous mode)
I/O ports • Input or output can be selected for each bits
USB function module • Conforming to the USB standard
• Corresponds mode of USB internal transceiver or external transceiver
• Supports control (endpoint 0), balk transmission (endpoint 1, 2),
interrupt (endpoint 3)
• Supports USB standard command and transaction class or vendor
command in firmware
• FIFO buffer for end point (128-byte/endpoint)
• Module input clock: 48MHz. Either self-powered or bus-powered mode
can be selected.
I 2 C bus interface (IIC2) • One channel
• Conforms to the Phillips I
2 C bus interface specification.
• Master/slave mode supported
• Continuous transmission/reception supported
• Either the I
2 C bus format or clock synchronous serial format is
selectable.
A/D converter • 10 bits±8 LSB, 8 channels
• Input range: 0 to AVcc (max. 3.6V)
U memory • Three independent read/write ports
 8-/16-/32-bit access from the CPU
 8-/16-/32-bit access from the DSP
 8-/16-bit access from the DMAC
• Total memory: 64-kbyte