Motorola ColdFire MCF5281 - Manual (Page 438)

UART Modules
23-18 Freescale Semiconductor
Using a 80-MHz internal bus clock and letting baud rate equal 9600, then
Eqn. 23-2
Therefore, UBG1n equals 0x01 and UBG2n equals 0x04.
23.4.1.2.2 External Clock
An external source clock (DTINn) passes through a divide-by-1 or 16 prescaler. If f
extc
is the external clock
frequency, baud rate can be described with this equation:
Eqn. 23-3
23.4.2 Transmitter and Receiver Operating Modes
Figure 23-18 is a functional block diagram of the transmitter and receiver showing the command and
operating registers, which are described generally in the following sections. For detailed descriptions, refer
to
Section 23.3, “Memory Map/Register Definition .”
Figure 23-18. Transmitter and Receiver Functional Diagram
23.4.2.1 Transmitter
The transmitter is enabled through the UART command register (UCRn). When it is ready to accept a
character, UART sets USRn[TXRDY]. The transmitter converts parallel data from the CPU to a serial bit
stream on UTXDn. It automatically sends a start bit followed by the programmed number of data bits, an
Divider
80MHz
32 x 9600
[ ]
------------------------------- 260 decimal
( )
0x0104 hexadecimal
( )
= = =
Baudrate
f
extc
(16 or 1)
--------------------- =
Receiver Shift Register
UART Command Register (UCRn) W
UART Status Register (USRn) R
Transmitter Shift Register
UART Mode Register 1 (UMR1n) R/W
UART Mode Register 2 (UMR2n) R/W
Transmitter Holding Register W
Receiver Holding Register 3
Receiver Holding Register 2
Receiver Holding Register 1 R
UART Receive
UART
Buffer (URBn)
(4 Registers)
UARTn
External
Interface
Transmit Buffer
(UTBn)
(2 Registers)
FIFO
URXDn
UTXDn
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3