Motorola ColdFire MCF5281 - Manual (Page 338)

Fast Ethernet Controller (FEC)
17-28 Freescale Semiconductor
Table 17-29. Receive Buffer Descriptor Field Definitions
Word Field Description
Offset + 0 15
E
Empty. Written by the FEC (=0) and user (=1).
0 The data buffer associated with this BD is filled with received data, or data reception has aborted
due to an error condition. The status and length fields have been updated as required.
1 The data buffer associated with this BD is empty, or reception is currently in progress.
Offset + 0 14
RO1
Receive software ownership. This field is reserved for use by software. This read/write bit is not
modified by hardware, nor does its value affect hardware.
Offset + 0 13
W
Wrap. Written by user.
0 The next buffer descriptor is found in the consecutive location
1 The next buffer descriptor is found at the location defined in ERDSR.
Offset + 0 12
RO2
Receive software ownership. This field is reserved for use by software. This read/write bit is not
modified by hardware, nor does its value affect hardware.
Offset + 0 11
L
Last in frame. Written by the FEC.
0 The buffer is not the last in a frame.
1 The buffer is the last in a frame.
Offset + 0 10–9 Reserved, must be cleared.
Offset + 0 8
M
Miss. Written by the FEC. This bit is set by the FEC for frames accepted in promiscuous mode, but
flagged as a miss by the internal address recognition. Therefore, while in promiscuous mode, you
can use the M-bit to quickly determine whether the frame was destined to this station. This bit is
valid only if the L-bit is set and the PROM bit is set.
0 The frame was received because of an address recognition hit.
1 The frame was received because of promiscuous mode.
Offset + 0 7
BC
Set if the DA is broadcast (FFFF_FFFF_FFFF).
Offset + 0 6
MC
Set if the DA is multicast and not BC.
Offset + 0 5
LG
Rx frame length violation. Written by the FEC. A frame length greater than RCR[MAX_FL] was
recognized. This bit is valid only if the L-bit is set. The receive data is not altered in any way unless
the length exceeds 2047 bytes.
Offset + 0 4
NO
Receive non-octet aligned frame. Written by the FEC. A frame that contained a number of bits not
divisible by 8 was received, and the CRC check that occurred at the preceding byte boundary
generated an error. This bit is valid only if the L-bit is set. If this bit is set, the CR bit is not set.
Offset + 0 3 Reserved, must be cleared.
Offset + 0 2
CR
Receive CRC error. Written by the FEC. This frame contains a CRC error and is an integral number
of octets in length. This bit is valid only if the L-bit is set.
Offset + 0 1
OV
Overrun. Written by the FEC. A receive FIFO overrun occurred during frame reception. If this bit is
set, the other status bits, M, LG, NO, CR, and CL lose their normal meaning and are zero. This bit
is valid only if the L-bit is set.
Offset + 0 0
TR
Set if the receive frame is truncated (frame length > 2047 bytes). If the TR bit is set, the frame must
be discarded and the other error bits must be ignored as they may be incorrect.
Offset + 2 15–0
Data
Length
Data length. Written by the FEC. Data length is the number of octets written by the FEC into this
BD’s data buffer if L equals 0 (the value is equal to EMRBR), or the length of the frame including
CRC if L is set. It is written by the FEC once as the BD is closed.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3