Motorola ColdFire MCF5281 - Manual (Page 63)

ColdFire Core
Freescale Semiconductor 2-17
All ColdFire processors inhibit interrupt sampling during the first instruction of all exception handlers.
This allows any handler to disable interrupts effectively, if necessary, by raising the interrupt mask level
contained in the status register. In addition, the ISA_A+ architecture includes an instruction (STLDSR)
that stores the current interrupt mask level and loads a value into the SR. This instruction is specifically
intended for use as the first instruction of an interrupt service routine that services multiple interrupt
requests with different interrupt levels. For more details, see ColdFire Family Programmer’s Reference
Manual.
2.3.3.1 Exception Stack Frame Definition
Figure 2-16 shows exception stack frame. The first longword contains the 16-bit format/vector word (F/V)
and the 16-bit status register, and the second longword contains the 32-bit program counter address.
The 16-bit format/vector word contains three unique fields:
• A 4-bit format field at the top of the system stack is always written with a value of 4, 5, 6, or 7 by
the processor, indicating a two-longword frame format. See
Table 2-6 .
• There is a 4-bit fault status field, FS[3:0], at the top of the system stack. This field is defined for
access and address errors only and written as zeros for all other exceptions. See
Table 2-7 .
32–47 0x080–0x0BC Next Trap # 0-15 instructions
48–63 0x0C0–0x0FC — Reserved
64–255 0x100–0x3FC Next Device-specific interrupts
1
Fault refers to the PC of the instruction that caused the exception. Next refers to the PC
of the instruction that follows the instruction that caused the fault.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSP
→
Format FS[3:2] Vector FS[1:0] Status Register
+ 0x4 Program Counter
Figure 2-16. Exception Stack Frame Form
Table 2-6. Format Field Encodings
Original SSP @ Time
of Exception, Bits 1:0
SSP @ 1st
Instruction of
Handler
Format Field
00 Original SSP - 8 0100
01 Original SSP - 9 0101
10 Original SSP - 10 0110
11 Original SSP - 11 0111
Table 2-5. Exception Vector Assignments (continued)
Vector
Number(s)
Vector
Offset (Hex)
Stacked
Program
Counter
Assignment
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3