Motorola ColdFire MCF5281 - Manual (Page 146)

Power Management
7-10 Freescale Semiconductor
7.3.2.17 Clock Module
In wait and doze modes, the clocks to the CPU, Flash, and SRAM will be stopped and the system clocks
to the peripherals are enabled. Each module may disable the module clocks locally at the module level. In
stop mode, all clocks to the system will be stopped.
During stop mode, there are several options for enabling/disabling the PLL and/or crystal oscillator (OSC);
each of these options requires a compromise between wakeup recovery time and stop mode power. The
PLL may be disabled during stop mode. A wakeup time of up to 200
μs is required for the PLL to re-lock.
The OSC may also be disabled during stop mode. The time required for the OSC to restart is dependent
upon the startup time of the crystal used. Power consumption can be reduced in stop mode by disabling
either or both of these functions via the SYNCR[STMPD] bits.
The external CLKOUT signal may be enabled during low-power stop (if the PLL is still enabled) to
support systems using this signal as the clock source.
The system clocks may be enabled during wakeup from stop mode without waiting for the PLL to lock.
This eliminates the wakeup recovery time, but at the risk of sending a potentially unstable clock to the
system. It is recommended, if this option is used, that the PLL frequency divider is set so that the targeted
system frequency is no more than half the maximum allowed. This will allow for any frequency overshoot
of the PLL while still keeping the system clock within specification.
In external clock mode, there are no wait times for the OSC startup or PLL lock.
During wakeup from stop mode, the Flash clock will always clock through 16 cycles before the system
clocks are enabled. This allows the Flash module time to recover from the low-power mode. Thus,
software may immediately continue to fetch instructions from the Flash memory.
The external CLKOUT output pin may be disabled in the low state to lower power consumption via the
DISCLK bit in the SYNCR. The external CLKOUT pin function is enabled by default at reset.
7.3.2.18 Edge Port
In wait and doze modes, the edge port continues to operate normally and may be configured to generate
interrupts (either an edge transition or low level on an external pin) to exit the low-power modes.
In stop mode, there is no system clock available to perform the edge detect function. Thus, only the level
detect logic is active (if configured) to allow any low level on the external interrupt pin to generate an
interrupt (if enabled) to exit the stop mode.
7.3.2.19 Watchdog Timer
In stop mode (or in wait/doze mode, if so programmed), the watchdog ceases operation and freezes at the
current value. When exiting these modes, the watchdog resumes operation from the stopped value. It is the
responsibility of software to avoid erroneous operation.
When not stopped, the watchdog may generate a reset to exit the low-power modes.
7.3.2.20 Programmable Interrupt Timers (PIT0, PIT1, PIT2 and PIT3)
In stop mode (or in doze mode, if so programmed), the programmable interrupt timer (PIT) ceases
operation, and freezes at the current value. When exiting these modes, the PIT resumes operation from the
stopped value. It is the responsibility of software to avoid erroneous operation.
When not stopped, the PIT may generate an interrupt to exit the low-power modes.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3