Motorola ColdFire MCF5281 - Manual (Page 330)

Fast Ethernet Controller (FEC)
17-20 Freescale Semiconductor
17.4.15 Descriptor Individual Upper Address Register (IAUR)
IAUR contains the upper 32 bits of the 64-bit individual address hash table. The address recognition
process uses this table to check for a possible match with the destination address (DA) field of receive
frames with an individual DA. This register is not reset and you must initialize it.
17.4.16 Descriptor Individual Lower Address Register (IALR)
IALR contains the lower 32 bits of the 64-bit individual address hash table. The address recognition
process uses this table to check for a possible match with the DA field of receive frames with an individual
DA. This register is not reset and you must initialize it.
IPSBAR
Offset:
0x10EC Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R OPCODE
PAUSE_DUR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 — — — — — — — — — — — — — — — —
Figure 17-14. Opcode/Pause Duration Register (OPD)
Table 17-18. OPD Field Descriptions
Field Description
31–16
OPCODE
Opcode field used in PAUSE frames. These read-only bits are a constant, 0x0001.
15–0
PAUSE_DUR
Pause Duration field used in PAUSE frames.
IPSBAR
Offset:
0x1118 Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
IADDR1
W
Reset — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — —
Figure 17-15. Descriptor Individual Upper Address Register (IAUR)
Table 17-19. IAUR Field Descriptions
Field Description
31–0
IADDR1
The upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast
address. Bit 31 of IADDR1 contains hash index bit 63. Bit 0 of IADDR1 contains hash index bit 32.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3