Motorola ColdFire MCF5281 - Manual (Page 120)

ColdFire Flash Module (CFM)
6-8 Freescale Semiconductor
6.3.4 Register Descriptions
The Flash registers are described in this subsection.
6.3.4.1 CFM Configuration Register (CFMCR)
The CFMCR is used to configure and control the operation of the CFM array.
Bits 10 -5 in the CFMCR register are readable and writable with restrictions.
0x1D_0014 CFMSACC S
0x1D_0018 CFMDACC S
0x1D_001C Reserved 2 S
0x1D_0020 CFMUSTAT Reserved 2 S
0x1D_0024 CFMCMD Reserved 2 S
1
S = Supervisor access only. User mode accesses to supervisor only addresses have no effect and result in a
cycle termination transfer error.
2 Addresses not assigned to a register and undefined register bits are reserved for expansion. Write accesses
to these reserved address spaces and reserved register bits have no effect.
15 11 10 9 8 7 6 5 4 0
Field — LOCK PVIE AEIE CBEIE CCIE KEYACC —
Reset 0000_0000_0000_0000
R/W R/W
Address IPSBAR + 0x1D_0000
Figure 6-4. CFM Module Configuration Register (CFMCR)
Table 6-4. CFMCR Field Descriptions
Bits Name Description
15–11 — Reserved, should be cleared.
10 LOCK Write lock control. The LOCK bit is always readable and is set once.
1 CFMPROT, CMFSACC, and CFMDACC register are write-locked.
0 CFMPROT, CMFSACC, and CFMDACC register are writable.
9 PVIE Protection violation interrupt enable. The PVIE bit is readable and writable. The
PVIE bit enables an interrupt in case the protection violation flag, PVIOL, is set.
1 An interrupt will be requested whenever the PVIOL flag is set.
0 PVIOL interrupts disabled.
8 AEIE Access error interrupt enable. The AEIE bit is readable and writable. The AEIE bit
enables an interrupt in case the access error flag, ACCERR, is set.
1 An interrupt will be requested whenever the ACCERR flag is set.
0 ACCERR interrupts disabled.
Table 6-3. CFM Register Address Map
IPSBAR Offset Bits 31–24 Bits 23–16 Bits 15–8 Bits 7–0 Access
1
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3