Motorola ColdFire MCF5281 - Manual (Page 334)

Fast Ethernet Controller (FEC)
17-24 Freescale Semiconductor
17.4.23 Transmit Buffer Descriptor Ring Start Registers (ETSDR)
ETSDR provides a pointer to the start of the circular transmit buffer descriptor queue in external memory.
This pointer must be 32-bit aligned; however, it is recommended it be made 128-bit aligned (evenly
divisible by 16). You should write zeros to bits 1 and 0. Hardware ignores non-zero values in these two bit
positions.
This register is undefined at reset and must be initialized prior to operation.
17.4.24 Receive Buffer Size Register (EMRBR)
The EMRBR is a user-programmable register that dictates the maximum size of all receive buffers. This
value should take into consideration that the receive CRC is always written into the last receive buffer. To
allow one maximum size frame per buffer, EMRBR must be set to RCR[MAX_FL] or larger. To properly
align the buffer, EMRBR must be evenly divisible by 16. To ensure this, bits 3–0 are forced low.
IPSBAR
Offset:
0x1180 Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
R_DES_START
0 0
W
Reset — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — —
Figure 17-22. Ethernet Receive Descriptor Ring Start Register (ERDSR)
Table 17-26. ERDSR Field Descriptions
Field Description
31–2
R_DES_START
Pointer to start of receive buffer descriptor queue.
1–0 Reserved, must be cleared.
IPSBAR
Offset:
0x1184 Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
X_DES_START
0 0
W
Reset — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — —
Figure 17-23. Transmit Buffer Descriptor Ring Start Register (ETDSR)
Table 17-27. ETDSR Field Descriptions
Field Description
31–2
X_DES_START
Pointer to start of transmit buffer descriptor queue.
1–0 Reserved, must be cleared.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3