Motorola ColdFire MCF5281 - Manual (Page 74)

ColdFire Core
2-28 Freescale Semiconductor
2.3.5.3 Standard One Operand Instruction Execution Times
2.3.5.4 Standard Two Operand Instruction Execution Times
Table 2-14. One Operand Instruction Execution Times
Opcode
Effective Address
Rn (An) (An)+ -(An) (d16,An) (d8,An,Xn*SF) xxx.wl #xxx
BITREV Dx 1(0/0) — — — — — — —
BYTEREV Dx 1(0/0) — — — — — — —
CLR.B 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) —
CLR.W 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) —
CLR.L 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) —
EXT.W Dx 1(0/0) — — — — — — —
EXT.L Dx 1(0/0) — — — — — — —
EXTB.L Dx 1(0/0) — — — — — — —
FF1 Dx 1(0/0) — — — — — — —
NEG.L Dx 1(0/0) — — — — — — —
NEGX.L Dx 1(0/0) — — — — — — —
NOT.L Dx 1(0/0) — — — — — — —
SCC Dx 1(0/0) — — — — — — —
SWAP Dx 1(0/0) — — — — — — —
TST.B 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0)
TST.W 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0)
TST.L 1(0/0) 2(1/0) 2(1/0) 2(1/0) 2(1/0) 3(1/0) 2(1/0) 1(0/0)
Table 2-15. Two Operand Instruction Execution Times
Opcode
Effective Address
Rn (An) (An)+ -(An)
(d16,An)
(d16,PC) (d8,An,Xn*SF)
(d8,PC,Xn*SF)
xxx.wl #xxx
ADD.L ,Rx 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0)
ADD.L Dy, — 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) —
ADDI.L #imm,Dx 1(0/0) — — — — — — —
ADDQ.L #imm, 1(0/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) —
ADDX.L Dy,Dx 1(0/0) — — — — — — —
AND.L ,Rx 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0)
AND.L Dy, — 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) —
ANDI.L #imm,Dx 1(0/0) — — — — — — —
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3