Motorola ColdFire MCF5281 - Manual (Page 384)

General Purpose Timer Modules (GPTA and GPTB)
20-16 Freescale Semiconductor
20.5.17 Pulse Accumulator Counter Register (GPTPACNT)
20.5.18 GPT Port Data Register (GPTPORT)
15 0
Field PACNT
Reset 0000_0000_0000_0000
R/W R/W
Address IPSBAR + 0x1A_001A, 0x1B_001B
Figure 20-19. Pulse Accumulator Counter Register (GPTPACNT)
Table 20-20. GPTPACR Field Descriptions
Bit(s) Name Description
15–0 PACNT Contains the number of active input edges on the PAI pin since the last reset.
Note: Reading the pulse accumulator counter registers immediately after an active
edge on the PAI pin may miss the last count since the input first has to be synchronized
with the bus clock.
To ensure coherent reading of the PA counter, such that the counter does not
increment between back-to-back 8-bit reads, it is recommended that only word (16-bit)
accesses be used. These bits are read anytime, write anytime.
7 6 5 4 3 0
Field — PORTT
Reset 0000_0000
R/W R/W
Address IPSBAR + 0x1A_001D, 0x1B_001D
Figure 20-20. GPT Port Data Register (GPTPORT)
Table 20-21. GPTPORT Field Descriptions
Bit(s) Name Description
7–4 — Reserved, should be cleared.
3–0 PORTT GPT port input capture/output compare data. Data written to GPTPORT is buffered
and drives the pins only when they are configured as general-purpose outputs.
Reading an input (DDR bit = 0) reads the pin state; reading an output (DDR bit = 1)
reads the latched value. Writing to a pin configured as a GPT output does not change
the pin state. These bits are read anytime (read pin state when corresponding
PORTTn bit is 0, read pin driver state when corresponding GPTDDR bit is 1), write
anytime.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3