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4 interrupt request level register (irlrn), 4 interrupt request level register (irlr n ) – Motorola ColdFire MCF5281 User Manual

Page 201

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Interrupt Controller Modules

Freescale Semiconductor

10-11

10.3.4

Interrupt Request Level Register (IRLRn)

This 7-bit register is updated each machine cycle and represents the current interrupt requests for each
interrupt level, where bit 7 corresponds to level 7, bit 6 to level 6, etc. This register output is combined
with similar outputs from INTC1 and eventually encoded into the 3-bit priority interrupt level driven to
the processor core.

10.3.5

Interrupt Acknowledge Level and Priority Register (IACKLPRn)

Each time an IACK is performed, the interrupt controller responds with the vector number of the highest
priority source within the level being acknowledged. In addition to providing the vector number directly
for the byte-sized IACK read, this 8-bit register is also loaded with information about the interrupt level
and priority being acknowledged. This register provides the association between the acknowledged
“physical” interrupt request number and the programmed interrupt level/priority. The contents of this
read-only register are described in

Figure 10-8

and

Table 10-11

.

7

2

1

0

Field

IRQ[7:1]

Reset

0000_0000

R/W

R

Address

IPSBAR + 0xC18, 0xD18

Figure 10-7. Interrupt Request Level Register (IRLRn)

Table 10-10. IRQn Field Descriptions

Bits

Name

Description

7–1

IRQ

Interrupt requests. Represents the prioritized active interrupts for each level.
0 There are no active interrupts at this level
1 There is an active interrupt at this level

0

Reserved

7

6

4

3

0

Field

LEVEL

PRI

Reset

0000_0000

R/W

R

Address

IPSBAR + 0xC19, 0xD19

Figure 10-8. IACK Level and Priority Register (IACKLPRn)

Table 10-11. IACKLPRn Field Descriptions

Bits

Name

Description

7

Reserved

MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3

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