Motorola ColdFire MCF5281 - Manual (Page 217)

Chip Select Module
Freescale Semiconductor 12-3
12.3 Chip Select Operation
Each chip select has a dedicated set of registers for configuration and control.
• Chip select address registers (CSARn) control the base address of the chip select. See
Section 12.4.1.1, “Chip Select Address Registers (CSAR0–CSAR6) ”.
• Chip select mask registers (CSMRn) provide 16-bit address masking and access control. See
Section 12.4.1.2, “Chip Select Mask Registers (CSMR0–CSMR6) ”.
• Chip select control registers (CSCRn) provide port size and burst capability indication, wait-state
generation, and automatic acknowledge generation features. See
Section 12.4.1.3, “Chip Select
Control Registers (CSCR0–CSCR6) ”.
CS0 is a global chip select after reset and provides relocatable boot ROM capability.
12.3.1 General Chip Select Operation
When a bus cycle is initiated, the device first compares its address with the base address and mask
configurations programmed for chip selects 0–6 (configured in CSCR0–CSCR6) and DRAM blocks 0 and
1 (configured in DACR0 and DACR1). If the driven address matches a programmed chip select or DRAM
block, the appropriate chip select is asserted or the DRAM block is selected using the specifications
programmed in the respective configuration register. Otherwise, the following occurs:
• If the address and attributes do not match in CSAR or DACR, the device runs an external
burst-inhibited bus cycle with a default of external termination on a 32-bit port.
• Should an address and attribute match in multiple CSCRs, the matching chip select signals are
driven; however, the chip select signals are driven during an external burst-inhibited bus cycle with
external termination on a 32-bit port.
• If the address and attribute match both DACRs or a DACR and a CSAR, the operation is undefined.
Table 12-3 shows the type of access as a function of match in the CSARs and DACRs.
12.3.1.1 8-, 16-, and 32-Bit Port Sizing
Static bus sizing is programmable through the port size bits, CSCR[PS]. See Section 12.4.1.3, “Chip Select
Control Registers (CSCR0–CSCR6) ” for more information. Figure 12-1 shows the correspondence
Table 12-3. Accesses by Matches in CSARs and DACRs
Number of CSCR Matches Number of DACR Matches Type of Access
0 0 External
1 0 Defined by CSAR
Multiple 0 External, burst-inhibited, 32-bit
0 1 Defined by DACRs
1 1 Undefined
Multiple 1 Undefined
0 Multiple Undefined
1 Multiple Undefined
Multiple Multiple Undefined
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3