Motorola ColdFire MCF5281 - Manual (Page 745)

Revision History
Freescale Semiconductor B-9
Chapter 8 Remove any references to the core watchdog timer being able to reset the device. It is only able to
interrupt the processor. Use the peripheral watchdog timer described in Chapter 18 if needing a
watchdog timer to reset the device.
Table 8-5/Page 8-6 CWCR[CWRI] bit description, change “...is programmed in the interrupt control register 7 (ICR7)...” to “...is
programmed in the interrupt control register 8 (ICR8)...”
Table 9-4/Page 9-7 In the table for MFD bit definition, footnote (1) equation should read:
Where f
sys(max)
is the maximum system frequency for the particular MCF5282 device (66MHz or 80MHz)
Section
10.3.6/Page 10-11
Include the following text in the section description and as a note in Figure 10-9.
“It is the responsibility of the software to program the ICRnx registers with unique and non-overlapping
level and priority definitions. Failure to program the ICRnx registers in this manner can result in
undefined behavior. If a specific interrupt request is completely unused, the ICRnx value can remain
in its reset (and disabled) state.”
Figure 10-6/Page
10-9
Interrupt Force Register Low (INTFRCLn) is illustrated as read-only in the figure. However, this register
should be read/write.
Table 10-14/Page
10-15
Change flag clearing mechanism for sources 24-26. They should read as follows:
Write ERR_INT = 1 after reading ERR_INT = 1
Write BOFF_INT = 1 after reading BOFF_INT = 1
Write WAKE_INT = 1 after reading WAKE_INT = 1
Table 12-7/Page
12-7
BAM bit field description, the first example should read “So, if CSAR0 = 0x0000 and CSMR0[BAM] =
0x0001” instead of “So, if CSAR0 = 0x0000 and CSMR0[BAM] = 0x0008”.
Table 10-2/Page
10-4
In footnote, remove mention of the SWIACK register, as it is not supported in the global IACK space.
Section
10.3.7/Page 10-16
Change last paragraph to: “In addition to the IACK registers within each interrupt controller, there are
global LnIACK registers. A read from one of the global LnIACK registers returns the vector for the highest
priority unmasked interrupt within a level for all interrupt controllers. There is no global SWIACK register.
However, reading the SWIACK register from each interrupt controller returns the vector number of the
highest priority unmasked request within that controller.”
Figure 15-1/Page
15-1
Change SDRAM address lines from A[31:0] to A[23:0].
Table 15-1/Page
15-3
NOP command entry. Replace “SRAS asserted” with “SDRAM_CS[1:0] asserted”
Table 15-5/Page
15-7
Add the following note to the DACRn[CBM] field description:
Note: It is important to set CBM according to the location of the command bit.
Section 16.5/Page
16-11
Remove last sentence in this section starting with “BCRn decrements...” since SAA bit is not supported.
Table B-7. Rev. 2.3 to Rev. 3 Changes (continued)
Location Description
f
sys
f
ref
2 MFD 2 +
( ) ×
2
RFD
--------------------------------------------- f
ref
2 MFD 2 +
( ) ×
f
sys max ( ) f
sys
f
sys max ( )
≤
;
≤
; =
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3