3 syncn, 5 memory map and registers, 3 syncn -4 – Motorola ColdFire MCF5281 User Manual
Page 372: 5 memory map and registers -4, 3 sync n

General Purpose Timer Modules (GPTA and GPTB)
20-4
Freescale Semiconductor
20.4.3
SYNCn
The SYNCn pin is for synchronization of the timer counter. It can be used to synchronize the counter with
externally-timed or clocked events. A high signal on this pin clears the counter.
20.5
Memory Map and Registers
See
for a memory map of the two GPT modules. GPTA has a base address of IPSBAR +
0x1A_0000. GPTB has a base address of IPSBAR + 0x1B_0000.
NOTE
Reading reserved or unimplemented locations returns zeroes. Writing to
reserved or unimplemented locations has no effect.
Table 20-3. GPT Modules Memory Map
IPSBAR Offset
Bits 7–0
Access
1
GPTA
GPTB
0x1A_0000
0x1B_0000
GPT IC/OC Select Register (GPTIOS)
S
0x1A_0001
0x1B_0001
GPT Compare Force Register (GPTCFORC)
S
0x1A_0002
0x1B_0002
GPT Output Compare 3 Mask Register (GPTOC3M)
S
0x1A_0003
0x1B_0003
GPT Output Compare 3 Data Register (GPTOC3D)
S
0x1A_0004
0x1B_0004
GPT Counter Register (GPTCNT)
S
0x1A_0006
0x1B_0006
GPT System Control Register 1 (GPTSCR1)
S
0x1A_0007
0x1B_0007
Reserved
2
—
0x1A_0008
0x1B_0008
GPT Toggle-on-Overflow Register (GPTTOV)
S
0x1A_0009
0x1B_0009
GPT Control Register 1 (GPTCTL1)
S
0x1A_000A
0x1B_000a
Reserved
(2)
—
0x1A_000B
0x1B_000b
GPT Control Register 2 (GPTCTL2)
S
0x1A_000C
0x1B_000c
GPT Interrupt Enable Register (GPTIE)
S
0x1A_000D
0x1B_000d
GPT System Control Register 2 (GPTSCR2)
S
0x1A_000E
0x1B_000e
GPT Flag Register 1 (GPTFLG1)
S
0x1A_000F
0x1B_000f
GPT Flag Register 2 (GPTFLG2)
S
0x1A_0010
0x1B_0010
GPT Channel 0 Register High (GPTC0H)
S
0x1A_0011
0x1Bb_0011
GPT Channel 0 Register Low (GPTC0L)
S
0x1A_0012
0x1B_0012
GPT Channel 1 Register High (GPTC1H)
S
0x1A_0013
0x1B_0013
GPT Channel 1 Register Low (GPTC1L)
S
0x1A_0014
0x1B_0014
GPT Channel 2 Register High (GPTC2H)
S
0x1A_0015
0x1B_0015
GPT Channel 2 Register Low (GPTC2L)
S
0x1A_0016
0x1B_0016
GPT Channel 3 Register High (GPTC3H)
S
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3