Motorola ColdFire MCF5281 - Manual (Page 164)

System Control Module (SCM)
8-12 Freescale Semiconductor
8.6.2 Features
Each bus transfer can be classified by its privilege level and the reference type. The complete set of access
types includes:
• Supervisor instruction fetch
• Supervisor operand read
• Supervisor operand write
• User instruction fetch
• User operand read
• User operand write
Instruction fetch accesses are associated with the execute attribute.
It should be noted that while the bus does not implement the concept of reference type (code versus data)
and only supports the user/supervisor privilege level, the reference type attribute is supported by the
system bus. Accordingly, the access checking associated with both privilege level and reference type is
performed in the IPS controller using the attributes associated with the reference from the system bus.
The SACU partitions the access control mechanisms into three distinct functions:
• Master privilege register (MPR)
— Allows each bus master to be assigned a privilege level:
– Disable the master’s user/supervisor attribute and force to user mode access
– Enable the master’s user/supervisor attribute
— The reset state provides supervisor privilege to the processor core (bus master 0).
— Input signals allow the non-core bus masters to have their user/supervisor attribute enabled at
reset. This is intended to support the concept of a trusted bus master, and also controls the
ability of a bus master to modify the register state of any of the SACU control registers; that is,
only trusted masters can modify the control registers.
• Peripheral access control registers (PACRs)
— Nine 8-bit registers control access to 17 of the on-chip peripheral modules.
— Provides read/write access rights, supervisor/user privilege levels
— Reset state provides supervisor-only read/write access to these modules
— Grouped peripheral access control registers (GPACR0, GPACR1)
— One single register (GPACR0) controls access to 14 of the on-chip peripheral modules
— One register (GPACR1) controls access for IPS reads and writes to the Flash module
— Provide read/write/execute access rights, supervisor/user privilege levels
— Reset state provides supervisor-only read/write access to each of these peripheral spaces
8.6.3 Memory Map/Register Definition
The memory map for the SACU program-visible registers within the System Control Module (SCM) is
shown in
Figure 8-7 . The MPR, PACR, and GPACRs are 8 bits in width.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3