Motorola ColdFire MCF5281 User Manual

Page 551

Queued Analog-to-Digital Converter (QADC)

Freescale Semiconductor

28-13

Table 28-6. QACR1 Field Descriptions

Bit(s)

Name

Description

CIE1

Queue 1 completion interrupt enable. Enables an interrupt request upon completion
of queue 1. The interrupt request is initiated when the conversion is complete for the
last CCW in queue 1.
1 Enable queue 1 completion interrupt.
0 Disable queue 1 completion interrupt.

PIE1

Queue 1 pause interrupt enable. Enables an interrupt request when queue 1 enters
the pause state. The interrupt request is initiated when conversion is complete for a
CCW that has the pause bit set.
1 Enable the queue 1 pause interrupt.
0 Disable the queue 1 pause interrupt.

SSE1

Queue 1 single-scan enable. Enables a single-scan of queue 1 after a trigger event
occurs. SSE1 may be set during the same write cycle that sets the MQ1 bits for one
of the single-scan queue operating modes. The single-scan enable bit can be written
to 1 or 0, but is always read as a 0, unless the QADC is in test mode. The QADC clears
SSE1 when the single-scan is complete.
1 Allow a trigger event to start queue 1 in a single-scan mode.
0 Trigger events are ignored for queue 1 single-scan modes.

12–8

MQ1n

Selects the operating mode for queue 1.

Table 28-7

shows the bits in the MQ1 field

which enable different queue 1 operating modes.

7–0

—

Reserved, should be cleared.

Table 28-7. Queue 1 Operating Modes

MQ1[12:8]

Operating Mode

00000

Disabled mode, conversions do not occur

00001

Software-triggered single-scan mode (started with SSE1)

00010

External-trigger rising-edge single-scan mode

00011

External-trigger falling-edge single-scan mode

00100