Motorola ColdFire MCF5281 - Manual (Page 755)

Freescale Semiconductor Index-7
interrupts
ColdFire Flash module 6-23
debug 2-21
, 30-37
FlexCAN 25-17
overview 10-1
PIT 19-7
prioritization 10-4
QADC
operation 28-68
sources 28-68
recognition 10-3
sources 10-13
vector determination 10-4
memory map 10-4
operation
general 10-2
low-power modes 7-9
registers
(IACKLPRn) 10-11
interrupt control (ICRnx) 10-12
interrupt force high/low (INTFRCHn, INTFRCLn) 10-9
interrupt pending high/low (IPRHn, IPRLn) 10-6
interrupt request level (IRLRn) 10-11
mask high/low (IMRHn, n) 10-7
J
JTAG
block diagram 31-1
electrical characteristics
boundary scan timing 33-25
features 31-2
initialization 31-9
nonscan chain operation 31-9
restrictions 31-9
instructions
BYPASS 31-9
CLAMP 31-9
ENABLE_TEST_CTRL 31-8
EXTEST 31-7
HIGHZ 31-8
IDCODE 31-7
LOCKOUT_RECOVERY 31-8
SAMPLE/PRELOAD 31-7
TEST_LEAKAGE 31-8
low-power modes 7-13
memory map 31-4
overview 31-1
registers
boundary scan 31-5
bypass 31-5
IDCODE 31-4
instruction shift (IR) 31-4
JTAG_CFM_CLKDIV 31-5
TEST_CTRL 31-5
TAP controller 31-6
timing diagrams
BKPT timing 33-27
boundary scan 33-26
test access port 33-26
test clock input 33-26
TRST timing 33-27
L
Listen-only mode 25-12
LOCKOUT_RECOVERY instruction 31-8
Lowest buffer transmitted first (LBUF) 25-21
Low-power modes
doze 7-6
peripheral behavior
chip configuration module 7-9
chip select module 7-7
clock module 7-10
ColdFire Flash module 7-7
, 7-13
core 7-6
debug 7-13
DMA controller 7-7
DMA timers 7-8
EPORT 7-10
Ethernet 7-9
FlexCAN 7-11
general purpose timers 7-11
GPIO 7-9
I
2
C 7-8
interrupt controller 7-9
JTAG 7-13
modules 7-8
programmable interrupt timers 7-10
QADC 7-11
QSPI 7-8
reset controller 7-9
SCM 7-7
SDRAM controller 7-7
SRAM 7-6
watchdog timer 7-10
run 7-5
stop 7-6
summary 7-13
wait 7-6
M
MAPGA package 32-9
Memory map
chip configuration module 27-3
clock module 9-5
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3