Motorola ColdFire MCF5281 - Manual (Page 59)

ColdFire Core
Freescale Semiconductor 2-13
For read-modify-write instructions, the pipeline effectively combines an embedded-load with a store
operation for a three-cycle execution time.
Figure 2-14. V2 OEP Register-to-Memory
The pipeline timing diagrams of Figure 2-15 depict the execution templates for these three classes of
instructions. In these diagrams, the x-axis represents time, and the various instruction operations are shown
progressing down the operand execution pipeline.
Operand Execution Pipeline
DSOC AGEX
Opword
Extension 1
Extension 2
Core Bus
Read Data
Core Bus
Address
Core Bus
Write
RGF
Data
Ax
d16
Ry x
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3