Motorola ColdFire MCF5281 - Manual (Page 262)

Signal Descriptions
14-22 Freescale Semiconductor
14.2.2.5 SDRAM Clock Enable (SCKE)
This output is the SDRAM clock enable.
This pin is configured as GPIO PSD0 in single-chip mode.
14.2.3 Clock and Reset Signals
The clock and reset signals configure the device and provide interface signals to the external system.
14.2.3.1 Reset In (RSTI)
Asserting RSTI causes the device to enter reset exception processing. When RSTI is recognized the
address bus, data bus, SIZ, R/W, AS, and TS are three-stated. RSTO is asserted automatically when RSTI
is asserted.
14.2.3.2 Reset Out (RSTO)
After RSTI is asserted, the PLL temporarily loses its lock, during which time RSTO is asserted. When the
PLL regains its lock, RSTO negates again. This signal can be used to reset external devices.
14.2.3.3 EXTAL
This input is driven by an external clock except when used as a connection to the external crystal when
using the internal oscillator.
14.2.3.4 XTAL
This output is an internal oscillator connection to the external crystal.
14.2.3.5 Clock Output (CLKOUT)
The internal PLL generates CLKOUT. This output reflects the internal system clock.
14.2.4 Chip Configuration Signals
14.2.4.1 RCON
If the external RCON signal is asserted, then various chip functions, including the reset configuration pin
functions after reset, are configured according to the levels driven onto the external data pins (see
Section 27.6, “Functional Description ”). The internal configuration signals are driven to reflect the levels
on the external configuration pins to allow for module configuration.
14.2.4.2 CLKMOD[1:0]
The state of the CLKMOD[1:0] pins during reset determines the clock mode after reset.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3