Motorola ColdFire MCF5281 - Manual (Page 503)

General Purpose I/O Module
Freescale Semiconductor 26-3
1. Although ports NQ, QA, QB, TA, and TB are not part of the ports module, they are included here for comprehensiveness.
Figure 26-2. MCF5280, MCF5281, and MCF5282 Ports Module Block Diagram
R/W / PE4
OE / PE7
SIZ0 / PE2 / SYNCB TA / PE6
TEA / PE5
D[7:0] / PD[7:0]
D[15:8] / PC[7:0]
D[23:16] / PB[7:0]
D[31:24] / PA[7:0]
BS[3:0] / PJ[7:4]
CS[3:0] / PJ[3:0]
PORT E
PORT D
PORT C
PORT B
PORT A
PORT J
TS / PE1 / SYNCA
TIP / PE0 / SYNCB
A[7:0] / PH[7:0]
A[15:8] / PG[7:0]
A[23:21] / PF[7:5] /
PORT H
PORT G
PORT F
DDATA[3:0] / PDD[7:4]
PST[3:0] / PDD[3:0]
ETXCLK / PEH[7]
ETXEN / PEH[6]
ETXD[0] / PEH[5]
ECOL / PEH[4]
ERXCLK / PEH[3]
ERXDV / PEH[2]
ERXD[0] / PEH[1]
ECRS / PEH[0]
ETXD[3] / PEL[7]
ETXD[2] / PEL[6]
ETXD[1] / PEL[5]
ETXER / PEL[4]
ERXD[3] / PEL[3]
ERXD[2] / PEL[2]
ERXD[1] / PEL[1]
ERXER / PEL[0]
EMDIO / PAS5 / URXD2
EMDC / PAS4 / UTXD2
CANRX / PAS3 / URXD2
CANTX / PAS2 / UTXD2
SDA / PAS1 / URXD2
SCL / PAS0 / UTXD2
QSPI_CLK / PQS2
QSPI_DIN / PQS1
QSPI_DOUT / PQS0
QSPI_CS[3:0] / PQS[6:3]
SRAS / PSD5
SCAS / PSD4
DRAMW / PSD3
SCKE / PSD0
SDRAM_CS[1:0] /
DTIN3 / PTC[3] / URTS1 / URTS0
DTIN2 / PTC[1] / UCTS1 / UCTS0
DTOUT2 / PTC[0] / UCTS1 / UCTS0
DTIN1 / PTD[3] / URTS1 / URTS0
DTOUT1 / PTD[2] / URTS1 / URTS0
DTIN0 / PTD[1] / UCTS1 / UCTS0
DTOUT0 / PTD[0] / UCTS1 / UCTS0
URXD1 / PUA[3]
UTXD1 / PUA[2]
URXD0 / PUA[1]
UTXD0 / PUA[0]
A[20:16] / PF[4:0]
SIZ1 / PE3 / SYNCA
PORT DD
PORT EH
PORT EL
PORT QB 1
PORT QA 1
PORT NQ
1
PORT AS
PORT TB 1
PORT TA 1
PORT SD
PORT QS
PORT TC
PORT TD
PORT UA
DTOUT3 / PTC[2] / URTS1 / URTS0
CS[6:4]
PSD[2:1]
AN3 / PQB3 / ANZ
AN2 / PQB2 / ANY
AN1 / PQB1 / ANX
AN0 / PQB0 / ANW
AN56 / PQA4 / ETRIG2
AN55 / PQA3 / ETRIG1
AN53 / PQA1 / MA1
AN52 / PQA0 / MA0
IRQ[7:1] / PNQ[7:1]
GPTA[3:0] / PTA[3:0]
GPTB[3:0] / PTB[3:0]
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3