Motorola ColdFire MCF5281 - Manual (Page 197)

Interrupt Controller Modules
Freescale Semiconductor 10-7
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10.3.2 Interrupt Mask Register (IMRHn, IMRLn)
The IMRHn and IMRLn registers are each 32 bits in size and provide a bit map for each interrupt to allow
the request to be disabled (1 = disable the request, 0 = enable the request). The IMRn is set to all ones by
reset, disabling all interrupt requests. The IMRn can be read and written. A write that sets bit 0 of the IMR
forces the other 63 bits to be set, disabling all interrupt sources, and providing a global mask-all capability.
Table 10-4. IPRHn Field Descriptions
Bits Name Description
31–0 INT Interrupt pending. Each bit corresponds to an interrupt source. The corresponding IMRHn bit
determines whether an interrupt condition can generate an interrupt. At every system clock, the
IPRHn samples the signal generated by the interrupting source. The corresponding IPRHn bit
reflects the state of the interrupt signal even if the corresponding IMRHn bit is set.
0 The corresponding interrupt source does not have an interrupt pending
1 The corresponding interrupt source has an interrupt pending
31 16
Field INT[31:16]
Reset 0000_0000_0000_0000
R/W R
15 1 0
Field INT[16:1] —
Reset 0000_0000_0000_0000
R/W R
IPSBAR + 0xC04, 0xD04
Figure 10-2. Interrupt Pending Register Low (IPRLn)
Table 10-5. IPRLn Field Descriptions
Bits Name Description
31–1 INT Interrupt Pending. Each bit corresponds to an interrupt source. The corresponding IMRLn bit
determines whether an interrupt condition can generate an interrupt. At every system clock, the
IPRLn samples the signal generated by the interrupting source. The corresponding IPRLn bit
reflects the state of the interrupt signal even if the corresponding IMRLn bit is set.
0 The corresponding interrupt source does not have an interrupt pending
1 The corresponding interrupt source has an interrupt pending
0 — Reserved, should be cleared.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3