1 pit control and status register (pcsrn), 1 pit control and status register (pcsr n, 1 pit control and status register (pcsr n ) – Motorola ColdFire MCF5281 User Manual
Page 363
Programmable Interrupt Timers (PIT0–PIT3)
Freescale Semiconductor
19-3
19.2.1
PIT Control and Status Register (PCSRn)
The PCSRn registers configure the corresponding timer’s operation.
User/Supervisor Access Registers
0x15_0004
0x16_0004
0x17_0004
0x18_0004
PIT Count Register (PCNTRn)
16
R
0xFFFF
1
Accesses to reserved address locations have no effect and result in a cycle termination transfer error.
2
User mode accesses to supervisor only addresses have no effect and result in a cycle termination transfer error.
IPSBAR
Offset:
0x15_0000 (PCSR0)
0x16_0000 (PCSR
1
)
0x17_0000 (PCSR
2
)
0x18_0000 (PCSR
3
)
Access: Supervisor
read/write
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
0
0
PRE
0
DOZE DBG
OVW
PIE
PIF
RLD
EN
W
w1c
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 19-2. PCSRn Register
Table 19-2. Programmable Interrupt Timer Modules Memory Map (continued)
IPSBAR Offset
Register
Width
(bits)
Access
1
Reset Value
Section/Page
PIT 0
PIT 1
PIT 2
PIT 3
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3