10 interrupt flag register (iflag), 10interrupt flag register (iflag) -28 – Motorola ColdFire MCF5281 User Manual
Page 498

FlexCAN
25-28
Freescale Semiconductor
The interrupt mask register contains two 8-bit fields: bits 15-8 (IMASK_H) and bits 7-0 (IMASK_L). The
register can be accessed by the master as a 16-bit register, or each byte can be accessed individually using
an 8-bit (byte) access cycle.
25.5.10 Interrupt Flag Register (IFLAG)
IFLAG contains one interrupt flag bit per buffer. Each successful transmission/reception sets the
corresponding IFLAG bit and, if the corresponding IMASK bit is set, will generate an interrupt.
This register contains two 8-bit fields: bits 15-8 (IFLAG_H) and bits 7-0 (IFLAG_L). The register can be
accessed by the master as a 16-bit register, or each byte can be accessed individually using an 8-bit (byte)
access cycle.
15
14
13
12
11
10
9
8
Field
BUF15M
BUF14M
BUF13M
BUF12
BUF11M
BUF10M
BUF9M
BUF8M
Reset
0000_0000
R/W
R/W
7
6
5
4
3
0
Field
BUF7M
BUF6M
BUF5M
BUF4M
BUF3M
BUF2M
BUF1M
BUF0M
Reset
0000_0000
R/W
R/W
Address
IPSBAR + 0x1C_0022
Figure 25-14. Interrupt Mask Register (IMASK)
Table 25-18. IMASK Field Descriptions
Bits
Name
Description
15–0
BUFn
M
IMASK contains one interrupt mask bit per buffer. It allows the CPU to designate which buffers will
generate interrupts after successful transmission/reception.
0 The interrupt for the corresponding buffer is disabled.
1 The interrupt for the corresponding buffer is enabled.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3