Motorola ColdFire MCF5281 - Manual (Page 271)

Signal Descriptions
Freescale Semiconductor 14-31
14.2.14.7 Debug Data (DDATA[3:0])
Debug data signals (DDATA[3:0]) display captured processor addresses, data and breakpoint status.
These pins can also be configured as GPIO PDD[7:4].
14.2.14.8 Processor Status Outputs (PST[3:0])
PST[3:0] outputs indicate core status, as shown below in Table 14-7 . Debug mode timing is synchronous
with the processor clock; status is unrelated to the current bus transfer.
These pins can also be configured as GPIO PDD[3:0].
14.2.15 Test Signals
14.2.15.1 Test (TEST)
This input signal is reserved for factory testing only and should be connected to VSS to prevent
unintentional activation of test functions.
Table 14-7. Processor Status Encoding
PST[3:0] Definition
0000 Continue execution
0001 Begin execution of an instruction
0010 Reserved
0011 Entry into user mode
0100 Begin execution of PULSE and WDDATA instruction
0101 Begin execution of taken branch
0110 Reserved
0111 Begin execution of RTE instruction
1000 Begin one-byte transfer on DDATA
1001 Begin two-byte transfer on DDATA
1010 Begin three-byte transfer on DDATA
1011 Begin four-byte transfer on DDATA
1100 Exception Processing
1101 Emulator-Mode Exception Processing
1110 Processor is stopped
1111 Processor is halted
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3