Motorola ColdFire MCF5281 - Manual (Page 414)

Queued Serial Peripheral Interface (QSPI)
22-10 Freescale Semiconductor
• 32 receive data bytes (receive data RAM)
The RAM is organized so that 1 byte of command control data, 1 word of transmit data, and 1 word of
receive data comprise 1 of the 16 queue entries (0x0–0xF).
NOTE
Throughout ColdFire documentation, the term word is used to designate a
16-bit data unit. The only exceptions to this appear in discussions of serial
communication modules such as QSPI that support variable-length data
units. To simplify these discussions, the functional unit is referred to as a
word regardless of length.
The user initiates QSPI operation by loading a queue of commands in command RAM, writing transmit
data into transmit RAM, and then enabling the QSPI data transfer. The QSPI executes the queued
commands and sets the completion flag in the QSPI interrupt register (QIR[SPIF]) to signal their
completion. As another option, QIR[SPIFE] can be enabled to generate an interrupt.
The QSPI uses four queue pointers. The user can access three of them through fields in QSPI wrap register
(QWR):
• New queue pointer (QWR[NEWQP])—points to the first command in the queue
• Internal queue pointer—points to the command currently being executed
• Completed queue pointer (QWR[CPTQP])—points to the last command executed
• End queue pointer (QWR[ENDQP]) —points to the final command in the queue
The internal pointer is initialized to the same value as QWR[NEWQP]. During normal operation, the
following sequence repeats:
1. The command pointed to by the internal pointer is executed.
2. The value in the internal pointer is copied into QWR[CPTQP].
3. The internal pointer is incremented.
Execution continues at the internal pointer address unless the QWR[NEWQP] value is changed. After each
command is executed, QWR[ENDQP] and QWR[CPTQP] are compared. When a match occurs,
QIR[SPIF] is set and the QSPI stops unless wraparound mode is enabled. Setting QWR[WREN] enables
wraparound mode.
QWR[NEWQP] is cleared at reset. When the QSPI is enabled, execution begins at address 0x0 unless
another value has been written into QWR[NEWQP]. QWR[ENDQP] is cleared at reset but is changed to
show the last queue entry before the QSPI is enabled. QWR[NEWQP] and QWR[ENDQP] can be written
at any time. When the QWR[NEWQP] value changes, the internal pointer value also changes unless a
transfer is in progress, in which case the transfer completes normally. Leaving QWR[NEWQP] and
QWR[ENDQP] set to 0x0 causes a single transfer to occur when the QSPI is enabled.
Data is transferred relative to QSPI_CLK, which can be generated in any one of four combinations of
phase and polarity using QMR[CPHA,CPOL]. Data is transferred with the most significant bit (msb) first.
The number of bits transferred defaults to 8, but can be set to any value between 8 and 16 by writing a
value into the BITSE field of the command RAM (QCR[BITSE]).
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3