Motorola ColdFire MCF5281 - Manual (Page 667)

IEEE 1149.1 Test Access Port (JTAG)
Freescale Semiconductor 31-3
When one module is selected, the inputs into the other module are disabled or forced to a known logic level
as shown in
Table 31-3 , in order to disable the corresponding module.
NOTE
The JTAG_EN does not support dynamic switching between JTAG and
BDM modes.
31.3.1.2 TCLK — Test Clock Input
The TCLK pin is a dedicated JTAG clock input to synchronize the test logic. Pulses on TCLK shift data
and instructions into the TDI pin on the rising edge and out of the TDO pin on the falling edge. TCLK is
independent of the processor clock. The TCLK pin has an internal pull-up resistor and holding TCLK high
or low for an indefinite period does not cause JTAG test logic to lose state information.
31.3.1.3 TMS/BKPT — Test Mode Select / Breakpoint
The TMS pin is the test mode select input that sequences the TAP state machine. TMS is sampled on the
rising edge of TCLK. The TMS pin has an internal pull-up resistor.
The BKPT pin is used to request an external breakpoint. Assertion of BKPT puts the processor into a halted
state after the current instruction completes.
31.3.1.4 TDI/DSI — Test Data Input / Development Serial Input
The TDI pin is the LSB-first data and instruction input. TDI is sampled on the rising edge of TCLK. The
TDI pin has an internal pull-up resistor.
The DSI pin provides data input for the debug module serial communication port.
31.3.1.5 TRST/DSCLK — Test Reset / Development Serial Clock
The TRST pin is an active low asynchronous reset input with an internal pull-up resistor that forces the
TAP controller to the test-logic-reset state.
Module selected BDM JTAG —
Pin Function —
BKPT
DSI
DSO
DSCLK
TCLK
TMS
TDI
TDO
TRST
TCLK
BKPT
DSI
DSO
DSCLK
Table 31-3. Signal State to the Disable Module
JTAG_EN = 0 JTAG_EN = 1
Disabling JTAG TRST = 0
TMS = 1
—
Disabling BDM — Disable DSCLK
DSI = 0
BKPT = 1
Table 31-2. Pin Function Selected
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3