Motorola ColdFire MCF5281 - Manual (Page 104)

Cache
4-6 Freescale Semiconductor
4.2.2 Access Control Registers (ACR0, ACR1)
The ACRs provide a definition of memory reference attributes for two memory regions (one per ACR).
This set of effective attributes is defined for every memory reference using the ACRs or the set of default
attributes contained in the CACR. The ACRs are examined for every processor memory reference not
mapped to the flash or SRAM memories.
The ACRs are 32-bit, write-only supervisor control register. They are accessed in the CPU address space
via the MOVEC instruction with an Rc encoding of 0x004 and 0x005. The ACRs can be read when in
background debug mode (BDM). Therefore, the register diagram,
Figure 4-3 , is shown as read/write. At
system reset, both registers are disabled with ACRn[EN] cleared.
NOTE
IPSBAR space should not be cached. The combination of the CACR
defaults and the two ACRn registers must define the non-cacheable attribute
for this address space.
Table 4-4. Cache Invalidate All as Defined by CACR
CACR
[DISI]
CACR
[DISD]
CACR
[INVI]
CACR
[INVD]
Configuration Operation
0 0 0 0 Split Instruction/
Data Cache Invalidate all entries in 1-KByte instruction
cache and 1-KByte data cache
0 0 0 1 Split Instruction/
Data Cache Invalidate only 1 KByte data cache
0 0 1 0 Split Instruction
Data Cache Invalidate only 1 KByte instruction cache
0 0 1 1 Split Instruction/
Data Cache No invalidate
1 0 x x Instruction Cache Invalidate 2 KByte instruction cache
0 1 x x Data Cache Invalidate 2 KByte data cache
BDM: 0x004 (ACR0)
0x005 (ACR1)
Access: Supervisor write-only
BDM read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
AB AM EN SM
0 0 0 0 0 0
CM BWE
0 0
WP
0 0
W
Reset – – – – – – – – – – – – – – – – 0 – – 0 0 0 0 0 0 – – 0 0 – 0 0
Figure 4-3. Access Control Registers (ACRn)
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3