Artesyn ATCA-8310 Installation and Use (May 2014) - Manual (Page 86)

Functional Description
ATCA-8310 Installation and Use (6806800M72E) 86
The data rate for the serial interface links is set to 32.768 Mbps and the number of active serial
links is reduced to two.
4.4.4 SRIO Interface
The TNETV3020 has two x1 SRIO interfaces which are cascaded to one chain with two
connections to the carrier board. The design is fault tolerant in a way that a single failure,
specifically the loss of one single DSP, does not cut the SRIO connection to functional DSPs.
The SRIO interfaces run with 1.25 Gb during boot operation and 2.5 Gb at normal operation.
4.4.5 RGMII Interface
Each TNETV3020 has a RGMII Ethernet interface which is connected to a dual PHY device
BCM5482S. The MDIO serial interface allows the DSP to configure the PHY devices and read
back PHY link information.
The BCM5482 offers an interface converter mode that supports RGMII-to-SGMII slave data
conversion. Each one of the PHY ports has a secondary SerDes that is used to perform
conversion.
4.4.6 DSP-FPGA
The DSP-FPGA is the main control unit on the DSP cluster. It controls all DSP functionality
including TSIP interface to the RTM and the power sequencing. The DSP-FPGA is connected to
service processor via SPI interface.
The configuration data are stored one SPI flash device. For update and recovery the SPP has
access to the configuration device.
Detailed functional informations are specified in detail within the FPGA Design Specification.
4.4.7 Module IPMC Interface
Each DSP module contains an EEPROM to storage FRU information. The interface is powered by
management power and connected to the IPMC via I2C.
Sensors and FRU information are specified in detail within the IPMC Design Specification.