Artesyn ATCA-8310 Installation and Use (May 2014) - Manual (Page 233)

Intelligent Peripheral Management Controller
ATCA-8310 Installation and Use (6806800M72E) 233
The FPGA is not reset. It receives the reset payload signal request and decides upon its reset
mask register (configurable by customer) which reset domains to reset:
 GPP
 Broadcom Switch
 DMC Base
 DMC #1
 DMC #2
 ARTM-8310
 Telecom clock
 SRIO
The IPMC will automatically switch the boot banks on SPP provided the failsafe logic is enabled
via OEM command.
When the fail safe logic is triggered as a result of the BMC Watchdog timeout, a System
Firmware Progress sensor SEL event is logged as follows:
 Event Data Byte 1: 0xA1 (System Firmware Hang)
 Event Data Byte 2: 0x00 (SPP CPU)
 Event Data Byte 3: 0xXX (Failed Boot Bank ID: 0=Bank A; 1=Bank B)
Fail Safe logic will make three attempts to boot the payload successfully. After three attempts,
the fail safe logic is automatically disabled and the boot bank is left in the original state (before
the payload was booted). In addition, this logic is only enabled upon a hard reset of the IPMC
firmware, a cold or warm IPMC reset will not enable this functionality.
Fail Safe is disabled by default and can be enabled with the IPMI command "Set Feature
Configuration".
7.14.2 SPP FPGA Watchdog
In addition to the BMC watchdog sensor, the SPP FPGA watchdog sensor is implemented with
Fail Safe support.