Artesyn ATCA-8310 Installation and Use (May 2014) - Manual (Page 175)

U-Boot
ATCA-8310 Installation and Use (6806800M72E) 175
The sub-commands are:
 list
to list all accessible FPGAs and their IDs
 select
to select a specific FPGA (for subsequent commands)
 read
to read a FPGA register. The access width can be specified using "read.b", "read.w" or "read.l"
for 1, 2 or 4 byte accesses).
 write
to write a FPGA register. The access width can be specified using "read.b", "read.w" or
"read.l" for 1, 2 or 4 byte accesses).
 dump
to dump all FPGA registers.
 Read
to read a FPGA register. The access width can be specified using "read.b", "read.w" or "read.l"
for 1, 2 or 4 byte accesses).
 update
to update the FPGA bitstream flash with an image at the specified memory address. A
successful upgrade requires a power cycle to become active.
The command requires an update file in "fri" format loaded to memory. Other files, or files
not matching to the currently selected FPGA are rejected.
6.2.1.6.1 Reset Control
The "rdc" command (for "reset domain control") can be used to control the various reset
domains on the ATCA-8310. The sub-commands are:
 list
Lists all reset domains and their status.
 set
Asserts reset for the specified domain.
 clear
De-asserts reset for the specified domain
 mask
Sets the reset mask for the specified domain. This makes the reset domain independent