Artesyn ATCA-8310 Installation and Use (May 2014) - Manual (Page 375)

CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72E) 375
0x6C TstPatCmpErrorCntR
eg Test Pattern Comparator Error Count Register (32bit) [Hw:
asyn, WAck3, RAck3]
After synchronization of the static pattern or the PRBS
receiver this registers counts bit errors. The counter sticks at
0xFFFFFF. It is cleared, when TstPatCmpRxPatEn bit changes
from 0 to 1. i.e. the receiver is re-enabled again.
TSIP to Serializer Converter Block (Tsip2SerBlk) [Hw: Cy0]
The Tsip2SerBlk picks the payload information from 60 TSIP-links and puts it on the 16 bit parallel
interface of the SerDes IP Block. For static test pattern transmission a supplementary channel is
provided. The supplementary channel has a data rate of 128kbit/s because of the transmission of 16
bits every 125 μs. Furthermore the Tsip2SerBlk controls the CRC insertion of the SerDes IP Block.
Access via SPI- bus from GlueFpga (occupies 256 Byte address area), hereof assigned to this block:
70...7F
Address Acronym Description
0x70 SerDesTrmCtrlReg Serdes Transmitter Control Register (8bit) [Hw: syn, WAck1,
RAck1]
A Serdes transmitter reset or resync can be initiated via this
register
0x71 SerDesTrmStatReg Serdes Transmitter Status Register (8bit) [Hw: syn , WAck1,
RAck1]
The Serdes transmitter status is shown
0x72 SupplTstPatTrmReg Supplemental Test Pattern Transmit Register (16bit) [Hw:
asyn, WAck2, RAck2]
Static Test Pattern from the Tsip2SerTstPatReg are
transmitted via the supplementary channel towards the serial
interface.
0x74 SupplTstPatCrcDisp
GenCtrlReg Supplemental Test Pattern, CRC and Disparity Generator
Control Register (8bit) [Hw: asyn, WAck2, RAck2]
This registers controls test pattern, CRC and Disparity
transmission
Table 8-174 Logic DSP FPGA Register Overview (continued)