Artesyn ATCA-8310 Installation and Use (May 2014) - Manual (Page 408)

CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72E) 408
This register monitors the Reset status of 10 DSPs.
8.4.2.7.3 DSP Watchdog Interrupt Status Register
Address: 0xA4, DspWdgStaReg
Width: 16 bit
This register monitors the Watchdog Interrupt status of 10 DSPs. If a Watchdog Interrupt
occurs, the respective bit is set. It can be reset by writing the respective bit in
DspWdgStaResReg.
Table 8-201 DSP Reset Status Register
Bit Acronym Type Description Default Pwr Soft
15...10 - - reserved undef - -
9 DspRes9 R 0b1: DspRes9, active if DSP9 is in reset 0b0 F F
8 DspRes8 R 0b1: DspRes8, active if DSP8 is in reset 0b0 F F
7 DspRes7 R 0b1: DspRes7, active if DSP7 is in reset 0b0 F F
6 DspRes6 R 0b1: DspRes6, active if DSP6 is in reset 0b0 F F
5 DspRes5 R 0b1: DspRes5, active if DSP5 is in reset 0b0 F F
4 DspRes4 R 0b1: DspRes4, active if DSP4 is in reset 0b0 F F
3 DspRes3 R 0b1: DspRes3, active if DSP3 is in reset 0b0 F F
2 DspRes2 R 0b1: DspRes2, active if DSP2 is in reset 0b0 F F
1 DspRes1 R 0b1: DspRes1, active if DSP1 is in reset 0b0 F F
0 DspRes0 R 0b1: DspRes0, active if DSP0 is in reset 0b0 F F
Table 8-202 DSP Watchdog Interrupt Status Register
Bit Acronym Type Description Default Pwr Soft
15...10 - - reserved undef - -
9 DspWdg9 R 0b1: DspWdg9, active if DSP9 Watchdog
Timer has expired 0b0 F F
8 DspWdg8 R 0b1: DspWdg8, active if DSP8 Watchdog
Timer has expired 0b0 F F