Artesyn ATCA-8310 Installation and Use (May 2014) - Manual (Page 409)

CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72E) 409
8.4.2.7.4 DSP Host Event Interrupt Status Register
Address: 0xA6, DspHevStaReg
Width: 16 bit
This register monitors the Host Event interrupt status of 10 DSPs. If a Host Event Interrupt
occurs, the respective bit is set. It can be reset by writing the respective bit in
DspHevStaResReg.
7 DspWdg7 R 0b1: DspWdg7, active if DSP7 Watchdog
Timer has expired 0b0 F F
6 DspWdg6 R 0b1: DspWdg6, active if DSP6 Watchdog
Timer has expired 0b0 F F
5 DspWdg5 R 0b1: DspWdg5, active if DSP5 Watchdog
Timer has expired 0b0 F F
4 DspWdg4 R 0b1: DspWdg4, active if DSP4 Watchdog
Timer has expired 0b0 F F
3 DspWdg3 R 0b1: DspWdg3, active if DSP3 Watchdog
Timer has expired 0b0 F F
2 DspWdg2 R 0b1: DspWdg2, active if DSP2 Watchdog
Timer has expired 0b0 F F
1 DspWdg1 R 0b1: DspWdg1, active if DSP1 Watchdog
Timer has expired 0b0 F F
0 DspWdg0 R 0b1: DspWdg0, active if DSP0 Watchdog
Timer has expired 0b0 F F
Table 8-202 DSP Watchdog Interrupt Status Register (continued)
Bit Acronym Type Description Default Pwr Soft
Table 8-203 DSP Host Event Interrupt Status Register
Bit Acronym Type Description Default Pwr Soft
15...10 - - reserved undef - -
9 DspHev9 R 0b1: DspHev9, active if DSP9 has signaled a
Host Event interrupt to the Control Unit 0b0 F F