Table 8-80, Reset terminal server register, Table 8-81 – Artesyn ATCA-8310 Installation and Use (May 2014) User Manual
Page 306: Reset release gpp register, Table 8-82, Reset spp register, Cpld and fpga, 15 reset control registers
CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72E)
306
8.2.2.3.15 Reset Control Registers
Table 8-80 Reset Terminal Server Register
Address: 0x12
Bit Description
Default
Access
7:0
Reset Terminal Server:
0x3C: Assert SOL_RST_ (drive low)
All other values: Drive SOL_RST_ high
0
SPP: r/w
Table 8-81 Reset Release GPP Register
Address: 0x13
Bit Description
Default
Access
7:0
Reset Release GPP:
Any write to this register releases GPP reset state machine.
Reset causes are stored but ignored until BIOS write access to this
register.
Note: Register needed to keep GPP in reset and to avoid resets
during critical BIOS code phase. See Project Wellbeck
-
GPP: w
Table 8-82 Reset SPP Register
Address: 0x13
Bit Description
Default
Access
7:0
Reset SPP:
0x3C: Assert SPP_HRESET_ (drive low for 50ms )
All other values: No SPP reset. SPP_HRESET_ is not asserted.
0
SPP: r/w