3 dsp fpga, 1 dsp fpga architectural overview, Figure 8-12 – Artesyn ATCA-8310 Installation and Use (May 2014) User Manual
Page 370: Dsp fpga overview, Cpld and fpga, Figure 8-12 dsp fpga overview
CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72E)
370
8.3
DSP FPGA
8.3.1
DSP FPGA Architectural Overview
Figure 8-12 Dsp Fpga Overview
TsipRcv0_D1
TsipRcv0_D2
TsipRcv0_D0
TsipRcv0_D3
TsipFsB0
TsipClkB0
TsipTrm 0_D1
TsipTrm 0_D2
TsipTrm 0_D0
TsipTrm 0_D3
TsipFsA0
TsipClkA0
Full TSIP
Interface
TsipRcv0_D1
TsipRcv0_D0
TsipFsB0
TsipClkB0
TsipTrm 0_D1
TsipTrm 0_D0
TsipFsA0
TsipClkA0
Half TSIP
Interface
0
10
11
Current
DSP
9..0
(One
TSIP
Each)
23
New
DSP
11..0
(Two
TSIP
Each)
Tsip0
24
47
New
DSP
11..0
(Two
TSIP
Each)
Tsip1
0
11
Spare
Tsip2Ser
Des2Tsip
SERDES
QUAD
0
Channel
0 (+1)
Clock and Frame Sync
Generator
(zero delay with PLL)
Base ID
Dsp, Phy Reset and
Dsp NMI
Dsp Power
Control
DSP, Phy Status and
Interrupt
Spi-Slave to
Wishbone
I2C Registers
(bit bang)
Testpattern
Generator
and
Comparator
9
Preparation
for new
DSPs
Spare
SCL
SDA
Reset NMI
Control
Host
Interrupts
Power
Control Status
MOSI
MISO
CS
DSPs
2nd
link
as
pre
par
a
tion
2nd
link
as
pre
par
a
tion
2.5G
Bit
Tx
2.5
GB
it
Rx
RTM
FPGA
Glue
FPGA
ACS
Clock
Gen.
Key:
Internal Status and
Interrupt
Diebel, Tieto 23.03.2010
CLK28M63636
FrameSync8k
CLK32M768
DspClks32M768
DspClkFeedBack
DspFS
RefClk
125MHz
RefClk
Wshbn2
SrdBs
AdrExtn
Serd
es
Clien
t
Inte
rface
Bus
Modul ID
MDIO
(bit bang)
MDC
MDIO
FPGA
Version
TdmClk32M768,
FrSync8k
TxClk125M
TxD
RxD
TxCtrlStat
RxCtrlStat
BID3..0
MID3..0
Wshb2Cfg
SPI
PhyRst
Dsp Timer
Clock (prep.)
Wishbone
clock only
Timer clock
Wishbone
Slave Bus
32Bit with
28.63636MHz
Destroy
Working
Reset
Control
ForceGolden
RxClk125M
Se
rd
es
R
es
et
PwGood
PwEn
Rsrv
3..0
Phy
Submodule
or eq. part of
baseboard
baseboard
baseboard