Cpld and fpga – Artesyn ATCA-8310 Installation and Use (May 2014) User Manual
Page 405
CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72E)
405
6...4
CoreSel
RW
specifies the C64x+ megamodule of the
DSP which is selected by the DspSel
bitfield:
0b000: SelMod0, specifies the C64x+
megamodule 0
0b001: Mod1Sel, specifies the C64x+
megamodule 1
0b010: Mod2Sel, specifies the C64x+
megamodule 2
0b011: Mod3Sel, specifies the C64x+
megamodule 3
0b100: Mod4Sel, specifies the C64x+
megamodule 4
0b101: Mod5Sel, specifies the C64x+
megamodule 5
0b110: reserved
0b111: AllModSel, specifies all C64x+
megamodules
0b000
X
X
Table 8-199 DSP Local Reset and NMI Control Register (continued)
Bit
Acronym Type
Description
Default
Pwr
Soft
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