Artesyn ATCA-8310 Installation and Use (May 2014) - Manual (Page 310)

CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72E) 310
Table 8-88 GPP Watchdog Control Register
Address: 0x19
Bit Description Default Access
1:0 Most significant bits of Watchdog time-out value. 2b11 GPP: r/w
6:2 Reserved 0 r
7 Watchdog Enable
Once the Watchdog is enabled the Watchdog stays enabled
until
PWR_GOOD is deassserted or GPP is reset. Watchdog time-out
may still be changed. 0 GPP: r/w1s
Table 8-89 SPP Watchdog Time-out Register
Address: 0x1A - 0x1B
Bit Description Default Access
15:0 Lower significant 16 bits of Watchdog time-out value.
Load 18 Bit Time-out value and (re)start watchdog. 0xFFFF SPP: r/w
Table 8-90 GPP Watchdog Time-out Register
Address: 0x1A - 0x1B
Bit Description Default Access
15:0 Lower significant 16 bits of Watchdog time-out value.
Load 18 Bit Time-out value and (re)start watchdog. 0xFFFF GPP: r/w