Artesyn ATCA-8310 Installation and Use (May 2014) - Manual (Page 246)

CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72E) 246
8.1.1.1 Unit Description
The Power-up logic required on ATCA 8310 resides in a CPLD. It implements these functions:
 Enable all onboard DC-DC converter
 Fulfill Power up timing sequence requirements
 Supervision of all onboard powers
 IPMC latch registers
 SPI Master interface to forward communication from IPMC to the Glue FPGA
 IPMC SPI Slave interface with two chip selects to communicate with the Glue FPGA and to
access CPLD Registers.
 SPI Slave interface to Glue FPGA to access CPLD registers. For example to update the CPLD
update via SPP.
 The CPLD clock uses the internal 22 MHz clock oscillator (+- 18%)
8.1.2 CPLD Registers
The CPLD Registers are accessible by the SPP via the CPLD SPI interface and or by the IPMC via
H8S SPI interface. The CPLD supports up to 32 registers.
Table 8-1 Register Default
Default Description
- Not applicable or undefined
0 or 1 Default value after CPLD_PWR_GOOD is valid.
Undef. Undefined value
: 0 or 1 Default value after deassertion of the reset signal .
Ext. External Reset Source. Default depends on external logic level.