Artesyn ATCA-8310 Installation and Use (May 2014) - Manual (Page 221)

Intelligent Peripheral Management Controller
ATCA-8310 Installation and Use (6806800M72E) 221
7.7 POST
POST is executed at IPMC startup when either a hard (blade physically extracted/reinserted) or
cold (IPMI Command) reset is performed. POST verifies the functionality of SRAM, IPMB-0,
EEPROM data storage, FRU-Information, and all devices (primarily sensors) attached to the
IPMC's private master-only I2C bus. A detailed description of POST tests are as follows:
1. FRU-Information - This test verifies that the FRU-Information is readable from the external
EEPROM where it is stored. Once read, each section's checksum is computed and
validated.
2. IPMB-0 - This test reads the ready signals coming from the I2C buffers. This test passes as
long as both ready signals are active and both IPMB busses (IPMB-A and IPMB-B) are
enabled.
3. EEPROM - This test verifies that the EEPROM contents are readable via I2C. Since the IPMC
stores its runtime and persistent data here, proper operation is crucial.
4. Master-Only I2C - This test verifies that all expected devices attached to the master-only
I2C bus are accessible.
7.8 FRU Inventory
The ATCA-8310 implements two intelligent FRU's (IPMC and MMC), 4 non-intelligent managed
FRU's (DMC modules and the Intel GPP) and one FRU which is not-managed at all (Mezzanine
Module at the RTM).
Every FRU provides its own FRU information (serial, part, DSP type, MAC addresses). Depending
on the presence of a module, its FRU information is visible or not.
Table 7-3 FRU information EEPROM Storage
I2C Address I2C bus Domain Purpose
0xA8 IPMC DMC module #0 FRU Information
0xAA IPMC DMC module #1 FRU Information
0xAC IPMC DMC module #2 FRU Information
0xA2 IPMC Intel GPP FRU Information
0xA2 IPMC Front blade FRU Information